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Chapter7 Latchs, Flip-Flops and Timers

Chapter7 Latchs, Flip-Flops and Timers

  • Latchs 锁存器
  • Flip-Flops 触发器
  • Timers 计时器
  • Bistable(双稳态) devices have two stable states, called SET and RESET. They are used as storage devices.
  • Monostable(单稳态) devices (monostable trigger, one-shot) have one stable state. They are used as timers.
  • Astable devices (multivibrator) (多谐振荡器) do not have stable state. They are used as waveform generators(波形发生器).

7.1 Lateches

  • The latch is a type of temporary device that hastwo stable states (bistable) for storing a bit and is normally placed in a category separate from that of flip-flops.
  • The difference between latches and flip-flops isthe method used for changing their states.
    • 简要理解，跟着时钟改变状态的是flip-flop，不跟着时钟改变状态的是锁存器

S-R Latch

active-HIGH S-R Latch

  • 只要S和R都设置为0，则触发器处于稳态，保持当前状态不变
  • S=1 R=0 则触发器置位，输出变为Q=1Q‾=0Q = 1 \quad \overline{Q} = 0
  • S=0 R=1 则触发器复位，输出变为Q=0Q‾=1Q = 0 \quad \overline{Q} = 1
  • S=1 R=1 无效状态，输出为Q=0Q‾=1Q = 0 \quad \overline{Q} = 1

Truth Table

S R QnQ^n (当前状态) Qn+1Q^{n+1} (下一状态) 说明
0 0 0 0 保持 (No Change)
0 0 1 1 保持 (No Change)
0 1 0 0 复位 (Reset)
0 1 1 0 复位 (Reset)
1 0 0 1 置位 (Set)
1 0 1 1 置位 (Set)
1 1 0 0* 不允许 (Invalid)
1 1 1 0* 不允许 (Invalid)

逻辑表达式

Qn+1=S‾⋅R‾Qn+SR‾⋅Qn‾+SR‾Qn=SR‾+S‾⋅R‾Qn=R‾(S+Qn)Q^{n+1} = \overline{S} \cdot \overline{R}Q^n + S\overline{R} \cdot\overline{Q^n} + S\overline{R}Q^n = S\overline{R} + \overline{S}\cdot \overline{R}Q^n = \overline{R} (S + Q^n)

在假设 S⋅R=0S \cdot R = 0 (即 S 和 R 不会同时为 1) ，即认为S 和 R 同时为高电平表示为 X (Don’t Care)的条件下，可以得出简化版逻辑

{Qn+1=S+R‾QnS⋅R=0\begin{cases} Q^{n+1} = S + \overline{R} Q^{n} \\ S \cdot R = 0 \end{cases}

The Gated S-R Latch

image-20250506205733698

直接给结论：

  1. EN=1EN = 1时，S（置位）和R（复位）才会起作用
  2. EN=0EN = 0时，无论S和R的值如何，Q和Q‾\overline{Q}的输出均表示不变

Q=EN⋅(S+R‾Qn)+EN‾QnQ = EN \cdot (S + \overline{R} Q^{n}) + \overline{EN} Q^n

The Gated D Latch

当EN=1EN = 1时，

Qn+1=DQ^{n+1} = D

  1. EN=1EN=1时，Q的值随D改变
  2. EN=0EN = 0时，Q的值被锁存，无论D怎么变，Q和Q‾\overline{Q}的值均不变

完整的逻辑表达式

Qn+1=EN⋅D+EN‾QnQ^{n+1} = EN \cdot D + \overline{EN} Q^n

image-20250506210917281

7.2 Edge-Triggered Flip-Flops

  • Flip-flops are synchronous bi-stable devices.
  • The term synchronous means that the output changes state only at a specified point on a triggering input called the clock (CLK) which is designated as a control input C; that is, changes in the output occur in synchronization with the clock.
  • An edge-triggered flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its input only at this transition of the clock.

Edge-Triggered S-R Flip-Flops

image-20250506211301532
  • When S is HIGH and R is LOW on the triggering edge of the clock pulse, Q is HIGH and the flip-flop is SET.
  • When S is LOW, R is HIGH, Q is LOW and flip-flop is RESET.
  • When S and R are both LOW, the output does not change from its prior state.
  • When S and R are both HIGH, it is an invalid condition.
image-20250506211350030 image-20250506211358099

Truth Table

image-20250506211416238 $$ \begin{cases} Q^{n+1} = S + \overline{R} Q^{n} \\ S \cdot R = 0 \end{cases} $$
  • Only change at the triggering edge (often rising edge) of CLK (clock pulse)
image-20250506211802007

A Method of Edge-Triggering

  • 非常巧妙，利用非门的延迟在时钟上升沿创造一个短暂的高电平，从而Enable Gate
image-20250506211733307

image-20250506211903055image-20250506211917290

The Edge-Triggered D Flip-Flop

image-20250506212001082 $$ Q^{n+1} = D $$
  • Only change at the triggering edge of CLK (clock pulse)

The Edge-Triggered J-K Flip-Flop

image-20250506212517217image-20250506212530152

Truth Table

J K CLK Q Q‾\overline{Q} 注释 (Comments)
0 0 ↑ Q0Q_0 Q0‾\overline{Q_0} 保持 (No change)
0 1 ↑ 0 1 复位 (RESET)
1 0 ↑ 1 0 置位 (SET)
1 1 ↑ Q0‾\overline{Q_0} Q0Q_0 翻转 (Toggle)

Logic Expression

Qn+1=JQn‾+K‾QnQ^{n+1} = J \overline{Q^n} + \overline{K} Q^n

Asynchronous Preset and Clear Inputs

  1. 异步性 (Asynchronous)：

    • 这两个输入之所以被称为“异步”，是因为它们不需要等待时钟脉冲 (CLK) 的有效边沿即可对触发器的输出状态产生影响。
    • 它们可以立即改变触发器的状态，优先于同步输入（如 J、K、D、T）和时钟信号。

  2. 预置 (Preset, PRE)：

    • 预置输入通常用于将触发器的输出 Q 强制设置为逻辑 ‘1’ (高电平)，同时其反向输出 Q‾\overline{Q} 被强制为逻辑 ‘0’。
    • 这个操作也常被称为“置位 (Set)”。

  3. 清除 (Clear, CLR)：

    • 清除输入通常用于将触发器的输出 Q 强制设置为逻辑 ‘0’ (低电平)，同时其反向输出 Q‾\overline{Q} 被强制为逻辑 ‘1’。
    • 这个操作也常被称为“复位 (Reset)”。

  4. 优先级 (Priority)：

    • 异步输入通常具有最高优先级。也就是说，如果一个有效的异步输入信号出现，它将覆盖所有其他同步输入和时钟信号的作用。
    • 在实际应用中，需要注意当 PRE‾\overline{PRE} 和 CLR‾\overline{CLR} 同时处于有效状态（例如，都为低电平）时的情况。这种状态通常是不允许的或会导致不确定的输出，具体行为取决于触发器的内部设计。

One-Shots

The one-shot is a monostable device, that is, it has only one stable state. A one-shot is normally in its stable state and will change to its unstable state only when triggered. Once it is triggered, the one-shot remains in its unstable state for a predetermined length of time and then automatically returns to its stable state. The time that the device stays in its unstable state determines the pulse width of its output.

  • A single narrow trigger pulse produces a single output pulse whose time duration is controlled by the RC time constant.

Vc(t)=VCC×(1−e−tτ)V_c(t) = V_{CC} \times (1 - e^{-\frac{t}{\tau}})

image-20250507100854329

image-20250507101256524

tw=0.7RCt_w = 0.7 RC

Nonretriggerable One-Shot

A nonretriggerable one-shot will not respond to any additional trigger pulses from the time it is triggered into its unstable state (fired) until it returns to its stable state.

image-20250507090407134

MSI: Nonretriggerable One-Shot 74121

  • The inputs A₁, A₂, and B are trigger inputs.
  • The RINTR_{INT} terminal connects to a internal timing resistor.
  • The CEXTC_{EXT} and REXTR_{EXT}/CEXTC_{EXT} terminals connect external timing capacitor and resistor.

image-20250507113041352

image-20250507113053463

With no external resistor and capacitor:

tw=30nst_w = 30ns

With external resistor and capacitor:

tw=0.7RCt_w = 0.7 RC

  • internal resistor RINT=2kΩR_{INT} = 2k\Omega

Retriggerable One-Shots

A retriggerable one-shot can be triggered before it times out.

image-20250507113105396

MSI: retriggerable One-Shot 74LS122

  • With no external resistor and capacitor: tw=45nst_w = 45ns
  • With external resistor and capacitor:tw=0.32RCEXT(1+0.7R)=0.32CEXT(R+0.7)t_w = 0.32 RC_{EXT} (1 + \frac{0.7}{R}) = 0.32 C_{EXT} (R + 0.7)

image-20250507113503721

Sequential Pulse Generator

image-20250507113522735

The 555 Timer

The 555 timer is a versatile and widely used device because it can be configured in three different modes as either a Schmitt trigger, a monostable multivibrator (one-shot), or an astable multivibrator (oscillator).

  • 三种主要工作模式
    • 非稳态多谐振荡器 (Astable Multivibrator) - 振荡器模式
    • 单稳态多谐振荡器 (Monostable Multivibrator) - 单次触发模式
    • 双稳态多谐振荡器 (Bistable Multivibrator) 或 施密特触发器 (Schmitt Trigger) 模式

四种基本状态

  • 这四种状态就对应里面那个S-R Latch的四种状态
    • SET
    • RESET
    • HOLD
    • INVALID
image-20250507103919104

image-20250507103941323

image-20250507104044588

image-20250507104144503

Monostable (One-Shot) Operation 单稳态触发器

  • 电路连接特征
    • (2) trigger 作为触发器输入，低电平有效（下降沿触发）
    • (6) Threshold 接RC中间 GND-C-(6)-R-VCC
    • (7) Discharge 也接RC中间

image-20250507104340881

Initial State (Prior to Triggering) 初始状态

Assume the initial state is

  • S-R Latch is in RESET state, and is holding (R/S pins are all LOW)
  • Trigger pin is HIGH
  • Discharge BJT Q1Q_1 is in the ON state
image-20250507105318499

When Triggered

  • A LOW (A Falling Edge) appears at Trigger pin

This will cause

  • S-R Latch is SET, Q becomes HIGH, Q‾\overline{Q} becomes LOW
  • Q1Q_1 is off, RC Circuit starts charging, u6=uC1↑u_{6} = u_{C1} \uparrow
image-20250507110634536

Return to Initial State

image-20250507110610509

When u6=uC1u_6 = u_{C1} reaches 23Vcc\frac{2}{3} V_{cc}, the S-R Latch is RESET, and then

  • Q1Q_1 is on, the capacitor C1C_1 quickly discharges through Q1Q_1
  • u6u_6 becomes low again, the S-R Latch holds at RESET state.
  • Remember the Conclusion

tw=1.1R1C1t_w = 1.1 R_1 C_1

image-20250507110700558

Invalid State

  • If the LOW continues appearing at Trigger after, the S-R latch will stay enter invalid state, which in most S-R Latch setups, the output Q is still SET.
  • Q will remain HIGH
  • 一直持续输出高电平
  • 电容持续充电直到 VccV_{cc}
  • 一般来说，不要出现这种情况

Default is non-retriggerable

  • 默认不可重复触发
  • 若需重复，需要添加一个比较复杂的外置电路（应该不会考）

Astable Operation

电路连接

image-20250507111400946

When the power is turned on

  • C1C_1 begins charging
image-20250507111534941

C1 Repeatedly switch between charging and discharging

image-20250507111741896

  • uC1u_{C1} 充到 23Vcc\frac{2}{3} V_{cc}时， S-R Latch复位，Q变LOW，放电三极管打开，C1开始放电
  • uC1u_{C1} 放到 13Vcc\frac{1}{3} V_{cc}时，S-R Latch复位，Q变LOW，放电三极管关闭，C1开始充电
  • C1C_1 充电时 VoutV_{out} 输出高电平，C1C_1 放电时 VoutV_{out} 输出低电平
  • 放电电路由R2R_2和C1C_1构成，充电电路由(R1+R2)(R_1 + R_2)和C1C_1构成，所以充/放电的时间常数就很显而易见
  • 最终结果：C1C_1 周期性地在充电/放电之间切换，VoutV_{out} 产生方波输出

tL=0.7(R1+R2)C1tH=0.7(R1+R2)C1t_L = 0.7(R_1 + R_2) C_1 \\ t_H = 0.7(R_1 + R_2) C_1

T=tL+tH=0.7(R1+2R2)C1T = t_L + t_H = 0.7(R_1 + 2R_2)C_1

f=1/T=10.7(R1+2R2)C1=1.44(R1+2R2)C1f = 1/T = \frac{1}{0.7(R_1 + 2R_2)C_1} = \frac{1.44}{(R_1 + 2R_2)C_1}

DutyCycle=tHT=tHtH+tL=R1+R2R1+2R2×100%>50%Duty Cycle = \frac{t_H}{T} = \frac{t_H}{t_H + t_L} = \frac{R_1 + R_2}{R_1 + 2R_2} \times 100\% > 50\%

Any Duty Cycle

tH=0.7R1C1t_H = 0.7 R_1 C_1
tL=0.7R2C1t_L = 0.7 R_2 C_1
T=0.7(R1+R2)C1T = 0.7 (R_1 + R_2) C_1
DutyCycle=tHT=R1R1+R2×100%Duty Cycle = \frac{t_H}{T} = \frac{R_1}{R_1 + R_2} \times 100\%

image-20250507112936354

施密特触发器模式 Schimitt Trigger/Bistable operation

A Simple Schmitt Triggerc

image-20250507102505114

Vt+=Vth(1+R1R2)Vt−=Vth(1+R1R2)−R1R2VDDV_{t+} = V_{th} (1 + \frac{R_1}{R_2}) \quad V_{t-} = V_{th}(1 + \frac{R_1}{R_2}) - \frac{R_1}{R_2} V_{DD}

迟滞宽度为

Vt+−Vt−=R1R2VDDV_{t+} - V_{t-} = \frac{R_1}{R_2} V_{DD}

假设理想状况高低电平的界限（阈值电压）是

Vth=VDD2V_{th} = \frac{V_{DD}}{2}

的话，那么有结论：迟滞宽度为

Vt+−Vt−=2R1R2VthV_{t+} - V_{t-} = 2\frac{R_1}{R_2} V_{th}

555 Timer Schimitt Trigger Operation

image-20250507102027711

  • 该模式下的电路连接
    • (2) trigger和(6) threshold接一起，作为电压输入uiu_i
  • 还记得滞回比较器么，这个分析方法差不太多很简单
    • 默认初始状态S-R Latch为RESET状态，初始电压ui<Vth−u_i < V_{th-}的情况下，逐渐增加uiu_i到超过上升阈值Vth+V_{th+}，然后再减小uiu_i到小于Vth+V_{th+}，回到RESET状态，就能把整个滞回曲线画出来了
  • 结论：

Vth+=23VccVth−=13VccV_{th+} = \frac{2}{3}V_{cc} \quad V_{th-} = \frac{1}{3} V_{cc}

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